The present invention relates to digital circuits and in particular to digital filters for decoding demodulated FM stereo signals into left and right channels. Additionally, the digital circuits of the present invention are particularly directed to simplified circuits for stereo channel decoding which are particularly amenable to fabrication on integrated circuit chips, either alone or on the same chip with other FM and/or AM signal processing circuitry.
In stereo FM broadcasts, three fundamental signals are transmitted. One part of the signal spectrum is allotted to transmission of a signal representing the sum of the left and right channels. Another part of the spectrum is allotted to the transmission of a signal representing the difference between the left and right channels. A third part of the standard FM stereo broadcast signal includes a 19 kHz pilot tone. This tone is used in demodulating the signal into left and right channel portions.
The present invention is particularly directed to that part of the circuitry which receives a demodulated signal which has already been digitized. As used herein and in the appended claims, the term digitized refers to the conversion of periodically sampled analog signals into equivalent binary number representations. Typically each analog sample is converted into a representation in terms of a sequence of binary digits. However, it is noted that while the analog samples are typically converted into a binary representation in which each position in the representation corresponds to a particular weighting factor which is a power of two, other number representational systems may be employed without departing from the spirit of the invention which is disclosed herein.
With respect to this invention, it is noted that it is directed to a circuit which receives already demodulated and digitized signals in which both left and right channel information is present. Accordingly, it is the function of the circuit of the present invention to produce digitized output signals representing extracted left channel and right channel information.
Conventionally, recovery of the 19 kHz pilot tone in FM receivers is accomplished using totally analog circuitry and design principles. These principles typically involve the use of a phase locked loop which locks onto the 19 kHz tone with a 38 kHz oscillator whose output is applied to a frequency divider which divides the frequency by a factor of two. Recovery of the pilot tone is essential for separating the left and right channel information signals.
However, it is not enough simply to provide a digital filter whose frequency response is such that the 19 kHz tone is passed through unattenuated while substantially all other frequencies are rejected. In order to provide the mechanism for producing the desired 38 kHz tone for ultimate channel separation, it is necessary that proper phase relationships in the signal output be present. Furthermore, while it is known that it is relatively easy to construct digital circuitry for performing operations such as addition and subtraction, it is also known that it is correspondingly much more difficult to provide digital circuitry for operations such as multiplication. Accordingly, one of the desirable features of an appropriate digital filter is an implementation in which a minimal number of multiplication operations is to be performed. In the preferable case in which the circuitry of the present invention is implemented on an integrated circuit chip, the problems of chip size and "real estate" also dictate that there be as few digital multiplication circuits as possible to conserve both space and power.